Transistor development have accelerated significantly in recent years particularly after the launching of “GaNpowIR” by “International Rectifier” and “eGaN FET” devices by “Efficient Power Conversion (EPC)” in 2010. These devices are particularly developed so as to cater for the low voltage market. These entities have developed highly efficient GaN high power transistor with breakdown voltages of about 600 V. More recently, Transphorm USA has also developed a 600 V semiconductor device using gallium-nitride (GaN) on silicon (Si).
Research efforts on the above devices have been spurred by the lower cost of using GaN on larger silicon substrates. As the silicon substrate plays an important role for GaN growth, ongoing research efforts have been focus on further reducing the cost of silicon compatible processes for making such devices. From an application point of view, silicon compatible processes developed based on these research efforts are not limited to low voltage applications, but may include high voltage applications, radio frequency (RF), wireless and light emitting diode applications. One such example relates to the research on p-type high electron mobility transistors (HEMT) which may lead to new generation of extraordinary high speed devices for various applications. In this context, there is a need for developing complementary metal oxide semiconductor (CMOS) process technology which may be compatible and applicable for fabrication of GaN based devices such as HEMT. However, several issues remain outstanding.
Accordingly, CMOS compatible metal remains poor or unsuitable contacts for GaN/AlGaN (aluminum-gallium-nitride) system when compared to gold-based (Au-based) processes. Yet, processes that utilize gold tend not to be cost-effective due to the use of gold material itself.
It is also known that CMOS compatible metal causes high ohmic resistance at source and drain (S/D) and this adversely affects devices performances.
Moreover, salicidation/germanidation of Si, Ge or SiGe materials may not be directly applied on GaN/AlGaN layers unlike typical Si-technology as self-aligning CMOS compatible processes remain unavailable due to the nature of GaN/AlGaN/metal systems which do not undergo silicidation/germanidation easily. Conventional self-aligned silicidation process requires metal deposition after a gate and spacer formation. This metal layer deposition is typically a blanket deposition. In such a process, the gate source and drain may be electrically shorted which is undesirable. After metal deposition, an annealing step may usually be required for the formation of a fused layer which tends to comprise a metal alloy. In the instance where GaN/AlGaN material is directly fused with a CMOS compatible metal, the fused metal layer tends to form only an ultrathin Ga(Al)GaN metal alloy layer at the interface. However, such an ultrathin Ga(Al)GaN metal alloy layer may be susceptible to removal by subsequent etching steps since most etchants tend to be able to remove the GaN thin alloyed layer. Thus, the direct alloying of metal in conventional self-aligning process, when combined with subsequent etching to remove any unreacted/non-fused metal, is not applicable for GaN/AlGaN based systems. In order to perform CMOS compatible processes with suitable isolation schemes, there is a need to develop a new device processing sequence.
Accordingly, there is a need to provide a method for fabricating semiconductor devices which overcomes, or at least ameliorates, one or more of the disadvantages described above.
To overcome the abovementioned issues, there is a need to develop an Au-free CMOS compatible self-aligning method for fabricating transistors (e.g. MOSFETs) using AlGaN/GaN HEMT based systems grown on bulk Si or silicon on insulator (SOI) substrates. Such a method may also be applicable to GaN-based HEMT structure on sapphire substrates or silicon carbide (SiC) substrate.
Particularly, there is a need to develop an intermediate platform or layer to enhance the compatibility of CMOS process technology on HEMT devices while using selected metal layering that could improve contact/ohmic resistance.